1. Field of the Invention
This invention relates to output buffers for digital electronic components such as analog-to-digital converters. More particularly, this invention relates to three-state output buffers for communicating with a multi-line bus.
2. Description of the Prior Art
There are many electronic components which must transfer a multi-bit output signal to a multi-line bus through which digital signals from other equipment must flow on a time-shared basis. To accommodate such other traffic, it has been the practice to employ a so-called three-state output buffer with the data-transferring component. Such a buffer in its "third state" presents a high output impedance to the bus, so that the traffic on the bus from other equipment will not be affected. When it is necessary for the component to deliver a digital signal to the bus, the buffer is switched from its third state to the data state, wherein output data is delivered from the component to the bus in the form of "ones" or "zeros". After delivery of the data, the output buffer is switched back to its high-impedance state.
For efficient data communications, it is important that switching between states be carried out at high speed. Conventionally, this has been achieved by the use of transistors which have been optimized for fast switching, such as those made for TTL logic. However, some components are made by IC processes which produce transistors incapable of such fast-switching operation. For example, processes have been developed to produce both linear transistors and inverted-mode transistors (so-called I.sup.2 L transistors) on the same chip, and in such compatible processes the transistors inherently have relatively long storage times which slows down their operation. Thus, there has developed a need for a three-state output buffer which uses the relatively slow transistors produced by such processes, and yet achieves fast operation in transferring data to the transmission bus.